Memory organization and output sequencer for a signal processor

Details Memory organization and output sequencer for a signal processor Memory organization and output sequencer for a signal processor

H - Electricity

04

J

363/14

H04J 3/12 (2006.01) H04Q 1/457 (2006.01)

Patent

CA 1287931

ABSTRACT A specialized tone receiver is capable of detecting tones on many different digital signal channels simultanously. A single memory is used to buffer incoming digital signals Independent write and read sequencers write samples into and read samples from the buffer memory, respectively. The write sequencer writes all samples corresponding to a given sample time at essentially the same time, while the read sequencer reads out all of the samples corresponding to a given channel of interest in reverse sequential chronological order (i.e., in the opposite order from the order the samples were written) beginning with the most current sample. A priority structure controls access to the buffer memory, with the read sequencer being granted a higher access priority than the write sequencer. A filtering algorithm symmetrical in time and executed by a digital signal processor controlled by the same microcode sequencer which controls the read sequencer is used to detect specific frequencies present in the read channel samples. A separate, slower processor performs time validation functions on a time scale which is extremely slow compared with the time scale at which frequency validation is performed. The specialized tone receiver is extremely fast, requires only a single, relatively small input buffer memory (e.g., 128 Kbytes for a 512 channel PCM bus), and is capable of detecting several different specialized signalling tones on all of the channels of a multiport multichannel PCM bus in very close to real time.

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