Memory patching circuit

Details Memory patching circuit Memory patching circuit

G - Physics

06

F

354/241

G06F 13/00 (2006.01) G06F 9/26 (2006.01) G06F 9/445 (2006.01)

Patent

CA 1070431

Abstract of the Disclosure A read only memory (ROM) patching arrangement is disclosed for providing valid output information when- ever ROM word locations containing invalid information are addressed. The disclosed arrangement uses a plurality of small capacity PROMs as a decoder to detect the receipt of each address word representing a defective ROM location. Upon each detection of a defective address, the decoder temporarily inhibits the output of the ROM and causes a small auxiliary memory to output valid program information as a substitute for that in the defective ROM location. A counter is used as a supplemental addressing source for both the decoder and the auxiliary memory. This increases the patching capability by subdividing the decoder and the auxiliary memory into 2n segments where n is the number of bits supplied by the counter.

263379

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