Memory patching circuit

Details Memory patching circuit Memory patching circuit

G - Physics

11

C

354/241

G11C 17/06 (2006.01) G06F 9/26 (2006.01) G06F 9/445 (2006.01)

Patent

CA 1062377

MEMORY PATCHING CIRCUIT Abstract of the Disclosure A ROM patching facility is described which permits any ROM address location containing defective information to be patched. New and updated program information is supplied to the system upon the detection of each address word that is to be patched. The disclosed equipment repatches one or more times a ROM address that has already been patched. Upon the detection of each such address, the program information associated with the most recent implemented patch is returned to the system. The disclosed equipment comprises a plurality of PROM decoders for detecting ROM addresses that are to be patched and for generating output signals representing each patched address, encoders for receiving the decoder output signals and for encoding each such signal into binary address information, and auxiliary memories controlled by the encoder address information for providing valid program information to the system upon each detection of a patched ROM address. - i -

263378

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