G - Physics – 06 – F
Patent
G - Physics
06
F
354/234
G06F 13/14 (2006.01) G06F 13/16 (2006.01) G06F 15/167 (2006.01)
Patent
CA 1256583
ABSTRACT OF THE DISCLOSURE The present invention pertains generally to the field of multiprocessor computer systems and more particularly to a method and apparatus for coordinating memory references to a shared main memory. This specification provides a memory interface and conflict resolution network for a multiprocessing system, and in particular for a multiprocessing system with four processors. The specification discloses among other things a four section memory with each section of member having a plurality of individually addressable memory banks. Associated with each section of memory is a section level conflict resolution network. Each processor in the system includes several ports which may generate reference requests to any one of the sections in the memory. A gating network is associated with each CPU such that each port may access any section of the memory but which restricts access to no more than one reference per CPU per clock period to each section of memory. To resolve conflicts between different ports in a CPU seeking access to the same section of memory a port conflict resolution circuit is provided for each CPU. The specification also discloses a two clock period conflicts resolution delay. During a first period conflicts between different ports in a CPU are resolved, and the prevailing reference request is forwarded to the section level conflicts resolution networks. During the second clock cycle, conflicts between different CPUs seeking access to the same banks in a particular section of memory are resolved.
512348
Cray Research Inc.
Gowling Lafleur Henderson Llp
LandOfFree
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