Memory refresh control system

Details Memory refresh control system Memory refresh control system

G - Physics

11

C

354/239

G11C 13/00 (2006.01) G06F 1/04 (2006.01) G11C 11/406 (2006.01) H03K 5/15 (2006.01)

Patent

CA 1136769

ABSTRACT OF THE DISCLOSURE In a memory refresh control system for refresh control of a memory having, as refresh addresses, addresses respectively corresponding to combinations of n+N bits, there are provided a refresh control circuit which yields, as refresh addresses, addresses respectively corresponding to combinations of n bits and generates, in a certain period of time, refresh clocks re- spectively corresponding to the abovesaid addresses for specifying 2n refresh times, a circuit which divides each of the refresh clock into 2N in terms of time and an overhead bit generator which is supplied with the divided clocks to produce successively addresses respectively corresponding to combinations of N bits for each divided clock. The n bits available from the refresh control circuit are added with the N bits generated by the overhead bit generator and then applied as an address of n+N bits to a memory, which is refreshed by the divided clock. The refresh clock divider is composed of monostable multivibrators of suitable time constants, and the overhead bit generator is formed by a counter.

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