Memory selection circuit

Details Memory selection circuit Memory selection circuit

G - Physics

11

C

G11C 8/00 (2006.01) G11C 8/10 (2006.01)

Patent

CA 2042432

ABSTRACT OF THE DISCLOSURE Memory selection circuit in which both the discharging time and the charging time of a cell selection line are reduced. For each line, the circuit includes a line driver connected to the line, an input stage for conditioning the line driver to activate the line connected thereto in response to an address signal, a controlled switching device for applying a discharging current to the selection line to speed up deactivation of the line, and means forming a part of the input stage for conditioning the controlled switching device to initiate application of the discharging current to the selection line in response to a change in the address signal. In one embodiment, the line driver is also turned on at an increased rate for a limited time following application of the address signal to speed up the activation of the line.

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