Memory selftest method and apparatus

Details Memory selftest method and apparatus Memory selftest method and apparatus

G - Physics

11

C

354/133, 354/224

G11C 29/00 (2006.01) G06F 7/58 (2006.01) G11C 29/20 (2006.01) G11C 29/36 (2006.01) G11C 29/44 (2006.01)

Patent

CA 1304821

Abstract A method and apparatus for testing each memory location of a memory device, the method comprising the steps of: generating each of the memory addresses corresponding to each memory location in a pseudo-random order; generating a pseudo-random series of data words; storing one of the data words at each memory location; reading each data word back from memory; regenerating the series of data words; and comparing each read data word to the corresponding regenerated data word. The invention features generating and storing a second series of data words, each data word being the inverse of the data words in the first series. The second series of data words are read from memory and compared to regenerated data. The invention also features a novel linear feedback shift register for generating the pseudo-random memory addresses and can generate the address zero. An accumulating register is utilized to store the approximate location of malfunctioning memory locations.

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