Memory sparing arrangement

G - Physics – 06 – F

Patent

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354/224, 354/225

G06F 11/00 (2006.01) G06F 13/00 (2006.01) G11C 29/00 (2006.01)

Patent

CA 1089104

MEMORY SPARING ARRANGEMENT Abstract A digital data processing arrangement for pro- viding automatic substitution of a spare memory module for a malfunctioning portion of the system memory is disclosed. The substitution takes place in a manner transparent to the software programs being run in the processing system. The system memory is organized as a plurality of memory modules, each having an identical number of individually addressable words. A particular module is enabled on receipt of an appropriate signal via a dedicated lead from the system processor unit, while a particular word within that module is specified by an address received via an address bus running to address decoder units at all modules. When the error detection and identification routines of the system processor determine that a particular module is malfunc- tioning, a hardware register and accompanying comparison logic are arranged such that a spare module is accessed whenever the particular malfunctioning module is subse- quently addressed. The approach does not diminish the available system memory address range after spare module substitution. Additionally, no memory reconfiguration is required after spare module substitution except for loading of the spare module itself whenever program memory substitution is involved.

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