G - Physics
06
F
G06F 12/02 (2006.01) G06F 12/06 (2006.01)
Patent
CA 2116985
The memory system disclosed herein can utilize a variable number of separately replaceable memory banks which can be implemented with memory elements, such as dynamic random access memory chips, which are of differing speeds and or sizes. The memory system implements an interleaving of memory addresses among the memory banks as a function of the number of banks actually present so that successive memory accesses are not unnecessarily delayed by the recovery times of the memory elements.
Andrade Albert T.
Burns Cynthia J.
Frangioso Ralph C. Jr.
Sullivan Timothy J.
Data General Corporation
Smart & Biggar
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