Memory system and related error detection and correction...

Details Memory system and related error detection and correction... Memory system and related error detection and correction...

G - Physics

06

F

354/223.1

G06F 11/10 (2006.01)

Patent

CA 1290459

ABSTRACT A memory system with error detection and correction functions is provided in which the memory, independent of its degree of parallelism, is organized in modules having 1 byte parallelism, each module having a section with 5 bit parallelism for storing SEC-DED codes related to the information stored in the module, and in which a fast memory, addressed by the data bytes and the related SEC-DED codes read from a memory module, act as a look-up table to provide at its output a data byte, corrected as a function of the SEC-DED code, a parity check bit for the corrected data, and further bits indicative of the presence of a corrected single error, and of the presence of uncorrectable multiple errors.

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