Memory system including a main memory and a cache memory

Details Memory system including a main memory and a cache memory Memory system including a main memory and a cache memory

G - Physics

11

C

354/237

G11C 7/00 (2006.01) G06F 12/08 (2006.01) G11C 15/00 (2006.01)

Patent

CA 1186804

- 15 - ABSTRACT MEMORY SYSTEMS A cache memory system is described that reduces cache interference during direct memory access block write operations to main memory. A control memory 36 within cache contains in a single location validity bits for each word in a memory block. In response to the first word transferred at the beginning of a direct memory access block write operation to main memory, all validity bits for the block are reset in a single cache cycle. Cache is thereafter free to be read by the central processor during the time that the remaining words of the block are written without the need for additional cache invalidation memory cycles.

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