Memory system with sector buffers

G - Physics – 06 – F

Patent

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Details

G06F 3/06 (2006.01) G06F 11/10 (2006.01) G11C 7/10 (2006.01) G11C 16/10 (2006.01) G11C 29/00 (2006.01)

Patent

CA 2589360

The invention relates to a memory system which is connected to a host system by means of a host bus (HB). Said system contains a memory controller (FC) having an internal memory (IR) and flash memory chips (F1..Fn) which are organised in individually deletable memory blocks. Said blocks contain a plurality of writeable and readable memory sectors, and the sectors are divided into sector sections which are secured by an ECC-word. The sectors are temporarily stored in the alternating sector buffers (SB1, SB2) in order to communicate with the host system and are transmitted between the sector buffers (SB1, SB2) and the flash memory chips(F1..Fn), by means of a direct- flash-access-unit (DFA), without having to be temporarily stored in the internal memory (IR) of the memory controller (FC).

L'invention concerne un système de mémoire relié à un système hôte par l'intermédiaire d'un bus hôte (HB), lequel système comprend un contrôleur de mémoire (FC) à mémoire interne (IR) et des puces de mémoire flash (F1..Fn) organisées en blocs de mémoire effaçables individuellement, lesquels blocs comportent une pluralité de secteurs de mémoire lisibles ou inscriptibles, divisés en sections de secteur sécurisées au moyen d'un mot CCE respectif. Selon la présente invention, ces secteurs sont stockés temporairement dans des tampons de secteur alternés (SB1, SB2) pour la communication avec le système hôte et transmis au moyen d'une unité d'accès flash direct (Direct Flash Access - DFA) entre les tampons de secteur (SB1, SB2) et les puces de mémoire flash (F1..Fn), sans être stockés temporairement dans la mémoire interne (IR) du contrôleur de mémoire (FC).

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