Memory using multiplexed row and column address lines

Details Memory using multiplexed row and column address lines Memory using multiplexed row and column address lines

G - Physics

11

C

352/82

G11C 5/02 (2006.01) G11C 8/00 (2006.01) G11C 8/10 (2006.01)

Patent

CA 1204510

- 14 - MEMORY USING MULTIPLEXED ROW AND COLUMN ADDRESS LINES Abstract A memory of rows and columns of memory cells uses a multiplexed input address buffer having output row-column address lines which are coupled to a multiplexer and to column decoders. The multiplexer is coupled to row address decoders and serves to selectively couple the address lines to the row decoders. The address lines typically first carry row address information and then column address information. The use of a common portion of the address lines to couple the address buffer to the column decoders and multiplexer tends to reduce the overall size of the memory and thereby increases yield and reduces cost.

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