G - Physics – 11 – C
Patent
G - Physics
11
C
354/246
G11C 11/40 (2006.01) G11C 11/24 (2006.01)
Patent
CA 1070851
ABSTRACT: The invention provides a solution for the refreshing organization in a main memory with dyna- mic information storage. In the case of a memory matrix, for example, each row of bit positions is addressed by first sub-address signals, with the, result that a refreshing operation is performed for the complete information of the relevant row. With- in a row bit position is addressed by second sub- address signals. A second memory is provided which comprises one word position for each bit row of the main memory. The second memory has a comparatively short memory cycle. During the first half of the "slow" memory cycle, a word of the second memory is addressed by the first sub-address signals and is filled with predetermined information. During the second half of the "slow" memory cycle, each time a next word of the second memory is addressed by the position of an address counter. The word is read. The output register is constructed as a counter; the information read is raised by 1 and is written back. A carry output signal of the out- put register can reserve the next "slow" cycle of the main memory for the execution of a refresh- ing operation at an address of the main memory which corresponds to the position of the address counter. - 28 -
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