G - Physics – 06 – F
Patent
G - Physics
06
F
G06F 7/08 (2006.01) G06F 7/36 (2006.01)
Patent
CA 2274282
A merge sorting apparatus comprises a comparison tournament circuit including comparison nodes, and a comparison control circuit for supplying to the corresponding comparison nodes validity flag information concerning the input data to each of the comparison nodes determined based on comparison results from the comparison nodes. The comparison control circuit comprises comparison result registers for retaining the comparison results, validity flag registers for retaining the validity flag information, and merge member registers for retaining information as to whether or not the input data to each of the input registers corresponding to respective pathways should be the object of comparison in the following data comparison processing. With this arrangement, contending readouts of record arrays from a memory can be reduced and the necessity to initialize each register is eliminated, thereby speeding merge sorting.
Gowling Lafleur Henderson Llp
Mitsubishi Denki Kabushiki Kaisha
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