Method and apparatus for an interleaved non-blocking packet...

Details Method and apparatus for an interleaved non-blocking packet... Method and apparatus for an interleaved non-blocking packet...

H - Electricity

04

L

H04L 12/56 (2006.01) G06F 12/06 (2006.01)

Patent

CA 2284231

Memory interleaving is performed to increase bandwidth of a common memory in a non-blocking switch. The switch receives packets from a plurality of ingress ports, stores the packets in the common memory, and forwards the packets to a plurality of egress ports. The common memory is physically divided into two banks to provide two way interleaving. Two way interleaving is performed by reading a packet to be forwarded to an egress port from one bank concurrently with writing a packet received from an ingress port to the other bank. The common memory is physically divided into four banks to provide four way interleaving. Four way interleaving is performed by concurrently reading and writing two even banks or two odd banks. Bank balancing techniques are also provided to keep the banks of the common memory at the same level of occupancy.

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