Method and apparatus for cascading frequency doublers

H - Electricity – 03 – B

Patent

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H03B 19/00 (2006.01) H03B 19/14 (2006.01) H03B 19/18 (2006.01)

Patent

CA 2281343

This invention provides a multistage frequency multiplier having a plurality of frequency doubters. Each doubter incorporates a three-terminal transistor device and is connected to an adjacent doubter via an interstage network. The network comprises a transmission line having its electrical parameters selected to achieve conjugate impedance matching at the intermediate harmonic frequency generated by the corresponding doubter. This network also includes a quarter-wavelength open-ended stub for suppressing a main input frequency component received by the corresponding frequency doubter. A shunt resistor on the transistor gate is preferably used to stabilize the network. This interstage network simplifies overall circuit topology to reduce total circuit size, and provides increased drive power levels to permit broader bandwidth and stabilize required output level from a local oscillator. This invention is particularly useful in high- speed, large-capacity communications systems and in microwave and millimeter-wave radar applications.

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