Method and apparatus for cascading frequency doublers

Details Method and apparatus for cascading frequency doublers Method and apparatus for cascading frequency doublers

H - Electricity

03

B

H03B 19/00 (2006.01) H01P 5/02 (2006.01) H03B 19/14 (2006.01) H03B 19/18 (2006.01) H03K 5/00 (2006.01) H03L 7/16 (2006.01)

Patent

CA 2244507

A topology for a multi-stage frequency multiplier, consisting only of frequency doublers, is disclosed employing direct phase matching between medium-power FETs. A prototype three-stage multiplier consists of the input-port network for the fundamental frequency matching, interstage matching networks for the second and the fourth harmonic signal, respectively, and the output-port network for the eighth harmonic matching. This approach, simplifying multiplier circuit configuration, is advantageous for compact local frequency source modules. The necessary output frequency power level is achieved without intermediate amplifiers when the final-stage output network is optimized.

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