Method and apparatus for clock recovery in digital...

Details Method and apparatus for clock recovery in digital... Method and apparatus for clock recovery in digital...

H - Electricity

04

J

H04J 3/06 (2006.01) H04L 7/027 (2006.01) H04L 7/033 (2006.01)

Patent

CA 2045166

PD89-0120 PATENT ABSTRACT OF THE DISCLOSURE A technique for recovering a clock from a digitally encoded communication signal uses a low-Q resonator and limiter for generating a coarse clock signal comprising a series of rectangular pulses at a frequency substantially equal to the clock (though subject to phase jitter), and a filter circuit, such as a phase-locked-loop ("PLL"), preferably employing a Sequential Phase/Frequency Detector, to reduce the jitter superimposed on the coarse clock signal, so as to yield a well-behaved clock signal. By using a Sequential Phase/Frequency Detector, acquisition-aid circuitry generally is not required for the PLL. FIGURE 1

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