Method and apparatus for controlling a programmable logic array

Details Method and apparatus for controlling a programmable logic array Method and apparatus for controlling a programmable logic array

H - Electricity

04

L

354/236, 354/237

H04L 15/34 (2006.01) G06K 15/10 (2006.01) H04Q 3/47 (2006.01)

Patent

CA 1087751

METHOD AND APPARATUS FOR CONTROLLING A PROGRAMMABLE LOGIC ARRAY Abstract of the Disclosure A circuit is described for controlling a programm- able logic array adapted for use with a communications terminal. The logic array includes an input AND-section defined by a plurality of addressable fields and an output OR-section. One field of the input section is addressed by an incoming address register selectively loaded with incoming data. A second field is addressed by a branch address register loaded with selective outputs of the output section thus providing program branching capabilities. Also, a loop counter and a clocked program counter address two additional fields of the input section. The loop counter facilitates program looping in the logic array while the program counter affords real time operational characteristics for the control circuit.

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