Method and apparatus for controlling power level during bist

Details Method and apparatus for controlling power level during bist Method and apparatus for controlling power level during bist

G - Physics

01

R

G01R 1/30 (2006.01) G01R 31/3187 (2006.01) G06F 1/32 (2006.01) G01R 31/3185 (2006.01)

Patent

CA 2226061

An improvement in a method of testing a digital circuit or system, having a plurality of scannable memory elements, in accordance with conventional BIST methods in which, at a reference clock, a test stimulus is shifted into the memory elements, the response of the elements is captured and the captured data is shifted out of the elements and analyzed, the improvement comprising controlling the average power consumption of the circuit during the test by suppressing clock pulses from the reference clock during phases of the test that do not require the maximum level of activity or in which the performance of the circuit is not to be evaluated; and, suppressing no clock pulses from the reference clock in phases of the test in which the performance of the circuit is to be evaluated, so that the conditions are substantially as those of normal mode of operation of the circuit.

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