G - Physics – 06 – F
Patent
G - Physics
06
F
354/241
G06F 12/02 (2006.01) G06F 9/46 (2006.01) G06F 12/08 (2006.01)
Patent
CA 2026236
ABSTRACT OF THE DISCLOSURE A processor which includes a plurality of sets of windowed registers, each set having a first plurality of IN registers and a second plurality of local registers, the IN registers of each set being addressable as the OUT registers of a logically-adjacent preceding set of registers, apparatus for indicating which set of registers is being addressed, a set of global registers which may be addressed with each of the sets of registers, an arithmetic and logic unit, a cache memory comprising a number lines at least equal to the total of the number of registers in an addressable set of windowed registers including the set of global registers and the IN registers of logically-adjacent set of registers addressable as OUT registers for a set of registers, and apparatus for changing the addresses of lines of the cache holding information presently designated in a particular window register set as information held in OUT registers to addresses designating the IN registers of the next register set, and apparatus for allowing the arithmetic and logic unit to access selected lines of the cachememory as processor registers.
Riches Mckenzie & Herbert Llp
Sun Microsystems Inc.
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