Method and apparatus for detecting linear phase error

Details Method and apparatus for detecting linear phase error Method and apparatus for detecting linear phase error

G - Physics

01

R

G01R 25/00 (2006.01) H03K 5/26 (2006.01) H04L 1/00 (2006.01)

Patent

CA 2538485

Disclosed herein is a method and apparatus used to detect phase error information between edges of an input data signal and a clock signal for use at ultra-high frequencies and where linear phase error information is required. This invention extends the usefulness of a given integrated circuit logic technology to twice the frequency range of application while maintaining the desired linear phase error measurement operation. Flip flops are used to sample the data input signal with the clocking signal and processing is done separately for rising and falling data edges. Analog recombination of phase error information from both edges is then done in a fashion that is not limited by the integrated circuit speed. This invention overcomes limitations of prior methods in that it operates in data applications, provides linear phase error information at very high phase-error bandwidth and can operate at the same maximum speed as the flip flop and logic process technology will allow by operating on bit cells that are a full 1-bit minimum rather than half-bit cells.

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