Method and apparatus for detecting retention faults in memories

G - Physics – 06 – F

Patent

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G06F 11/14 (2006.01) G01R 31/3183 (2006.01) G11C 29/50 (2006.01)

Patent

CA 2113863

- 16- METHOD AND APPARATUS FOR DETECTING RETENTION FAULTS IN MEMORIES Abstract The present invention is directed to a method for detecting retention faults in each of a plurality of read/write memory elements (121 - 12z), arranged in a plurality of banks (141 - 14k) coupled in daisy chain fashion. Retention faults are detected, in accordance with the method, by signaling the banks in sequence, at each of three separate intervals, to cause the memory elements in each bank to execute a first, second and third sequence of read and/or write instructions. Execution of the second sequence of read and/or write operations is delayed so each memory element can be read after a prescribed interval to detect a first bit pattern written in each memory at the end of the first sequence. Similarly, execution of the third sequence of read and/or write operations is delayed so each memory element can be read after a prescribed interval to detect a second bit, complementary to the first pattern, written in the memory element at the end of the second sequence. By delaying theexecution of the second and third sequences of read and/or write operations, retention faults, if any, can manifest themselves.

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