Method and apparatus for digital data synchronization

H - Electricity – 04 – J

Patent

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H04J 3/06 (2006.01) H04J 3/07 (2006.01) H04J 3/16 (2006.01) H04Q 11/04 (2006.01)

Patent

CA 2462902

Synchronization and desynchronization of a data signal transported in a synchronous frame across a synchronous communications network, such as SONET/SDH, reduces waiting-time jitter. A timing estimate (F) indicative of a relationship between a data rate (f1) of the data signal and a reference frequency (f2) of the synchronous communications network is calculated and communicated through the synchronous communications network, for example in the Synchronous Payload Envelope of a SONET frame. The data signal is recovered using a desynchronizer Phase-Locked Loop steered by the timing estimate (F). The timing estimate (F) can be any one or more of: a ratio between the data rate (f1) and the reference frequency (f2); a difference between the data rate (f1) and the reference frequency (f2); and a phase difference between a recovered data clock signal associated with the data rate (f1) and a reference clock signal associated with the reference frequency (f2).

L'invention concerne un procédé et un appareil permettant de synchroniser et désynchroniser des données numériques. Une valeur multibit est déterminée et communiquée avec un bloc de données à un débit binaire f¿1? et mappée dans un train de données synchrones à un débit binaire f¿2? dans un synchroniseur. Le débit binaire f¿1? peut être dérivé des valeurs multibit d'un désynchroniseur. L'invention concerne également un procédé permettant de convertir des signaux asynchrones en signaux synchrones par adaptation de débit, ce qui réduit la gigue due à un temps d'attente.

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