Method and apparatus for error control in asynchronous...

Details Method and apparatus for error control in asynchronous... Method and apparatus for error control in asynchronous...

H - Electricity

04

L

354/222

H04L 1/00 (2006.01)

Patent

CA 1130008

ABSTRACT METHOD & APPARATUS FOR ERROR CONTROL IN ASYNCHRONOUS COMMUNICATIONS Error control, in the form of a modulo 2 division re- mainder checksum is added to a packet of reformatted asynchronous characters prior to transmission over a data link connecting two data devices such as a host computer and a teletype terminal. At one end of the link, data in asynchronous form, such as ASCII code, comprising seven data bits, start and stop bits, and a parity bit, is originated by one data device. The start, stop and parity bits of each character are eliminated. The remaining data bits for a selected number of characters are then grouped together to form a data grouping and the checksum and other control in- formation bits added, forming an information packet. The information packet is then divided into sections or groups of eight bits. Start and stop bits are added to each group, forming ten bit characters. The ten bit characters are then transmitted over the data link in standard asynchronous format. The process is carried out in reverse at the other end of the link, resulting in the other data device receiving the data in the form originated by the first data device. Sophisticated error control techniques thus may be implemented in asynchronous communications without detrimentally affecting the data capacity on the channel.

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