Method and apparatus for generating and synchronizing...

Details Method and apparatus for generating and synchronizing... Method and apparatus for generating and synchronizing...

H - Electricity

04

L

H04L 7/033 (2006.01) H03L 7/06 (2006.01) H03L 7/07 (2006.01)

Patent

CA 2388901

Methods and systems for generating and synchronizing multiple clocks are disclosed herein that have extremely low skew across multiple channels and latency that is both minimal and well-defined. A phase-locked loop circuit generates a plurality of clock signals to synchronize channel circuits that receive core data streams. The channel circuits convert the core data streams into serial data streams. The phase-locked loop circuit or another phase-locked loop circuit generates a core clock signal for the registered transfer of the core data streams to the channel circuits. One or more of the plurality of clock signals may be distributed to the channel circuits by a register-to-register transfer.

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