Method and apparatus for generating timing phase error...

Details Method and apparatus for generating timing phase error... Method and apparatus for generating timing phase error...

H - Electricity

04

L

340/74

H04L 7/00 (2006.01) H04L 7/02 (2006.01) H04L 27/227 (2006.01) H04L 27/00 (2006.01)

Patent

CA 1120121

D-21,734 METHOD AND APPARATUS FOR GENERATING TIMING PHASE ERROR SIGNALS IN PSK DEMODULATORS By Robert J. Tracey Stevan D. Bradley William F. Hartley ABSTRACT OF DISCLOSURE A circuit arrangement for combining a measure of the signal phase error for a received data signal in a PSK demodulator with a measure of the di- rection of rotation of the receive data signal phasor between adjacent sample times for producing a timing phase error signal for controlling the phase of a local clock timing signal in the demodulator. In a demodulator producing a digital word defining differences between the phases of decoded phasors at adja- cent sample times, a binary bit Dk of the digital word may define the direction of rotation of the received signal phasor between the adjacent sample times. Sample values of the signal phase error signal in the demodulator are quantized into single binary bits Ek indicating the sense of the signal phase error at sample times. In one circuit arrangement, binary bits Ek and Dk are combined in an exclusive-OR gate for producing a binary timing phase error bit Mk. In a demodulator where phase differences are consecutively numbered clockwise in straight binary, the output of the exclusive-OR gate is inverted for producing binary timing phase error bits Mk. In another circuit arrangement, binary bits Ak and Bk indicating the sense of the in-phase and quadrature-phase signal com- ponents for decoded phasors at a number of sample times are logically combined with signal phase error bits Ek for producing binary timing phase error bits Mk at sample times.

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