Method and apparatus for identifying faulty address decoders

G - Physics – 11 – C

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354/224

G11C 29/02 (2006.01) G06F 11/16 (2006.01)

Patent

CA 1086863

Abstract of Disclosure: A central control unit is connected via a common bus system to a number of function units, each of which is furnished with duplicated address decoders in order to ensure reliable selection of units. If, in response to an address which is sent out by the control unit, a signal is emitted by only one of the decoders belonging to a function unit a recording is made in a memory de- vice corresponding to that decoder to indicate an erroneous condition. If, on the other hand, signals are emitted by both decoders a check signal is returned to the control unit, the absence of the check signal indicating that either one of the decoders belonging to the addressed function unit is faulty. Error recordings are read out from the respective memory device by subsequent addressing of the units, the read out from the memory device belonging to the one address decoder being effected by the signal emitted by the other decoder and vice versa.

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