Method and apparatus for implementing a bus protocol

Details Method and apparatus for implementing a bus protocol Method and apparatus for implementing a bus protocol

G - Physics

06

F

354/234

G06F 13/36 (2006.01) G06F 13/378 (2006.01) G06F 13/42 (2006.01) G06F 11/10 (2006.01)

Patent

CA 1273117

ABSTRACT OF THE DISCLOSURE A computing system is disclosed which uses a system busy signal on its system bus to help control access to said bus. One or more requesters can generate a request signal when the system busy signal is not asserted. System busy is asserted along with the request signal(s) and remains asserted until all requesters which generated a request signal have gained access to the bus in order of priority. A freeze signal is generated on the system bus during the address phase of an instruction and a wait signal is generated during each data transfer in the data phase of an instruction. The freeze signal may be generated by a memory control unit, a memory module or a requester.

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