G - Physics – 06 – F
Patent
G - Physics
06
F
354/233
G06F 13/28 (2006.01)
Patent
CA 1315890
ABSTRACT OF THE DISCLOSURE In a computer system, a plurality of input/output processors (IOP's) are connected via an asynchronous input/output bus, called an "SPD" bus, to one side of an input/output interface controller (IOIC). The other side of the IOIC is connected to a storage controller (SC) via a synchronous bus called an "adapter" bus. The SC is connected to a common system memory and possibly also to an instruction processing unit. The SPD bus, which comprises three sub-buses and a control bus, conducts signals between each IOP and the IOIC in an asynchronous "handshaking" manner. The adapter bus, which comprises two sub-buses and a control bus, conducts signals between the IOIC and the SC in a synchronous manner. The IOIC, interconnected between the SPD bus and adapter bus, functions as a buffer between the faster synchronous bus and the slower asychronous bus. The IOIC also comprises at least one shared DMA facility for executing DMA storage operations requested by the IOP's via the SPD bus. Each shared DMA facility includes a buffer for control information and data to be transmitted between the SC and one of the IOP's and a bus interface coupled to the buffer, to the adapter bus and to the SPD bus for independently transferring the control information and data between the buffer and the SC, on one hand, via the adapter bus, and between the buffer and the one IOP, on the other hand, via the SPD bus. In this manner, the SPD bus can be released for utilization by other IOP's connected thereto during a period of "storage latency" after a DMA storage operation has been initiated by one IOP.
598603
Chisholm Douglas R.
Iseminger Robert G.
Kelley Richard A.
Leung Wan L.
Moyer James T.
International Business Machines Corporation
Saunders Raymond H.
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