Method and apparatus for interconnecting processors in a...

Details Method and apparatus for interconnecting processors in a... Method and apparatus for interconnecting processors in a...

G - Physics

06

F

354/233

G06F 13/40 (2006.01) G06F 15/16 (2006.01) G06F 15/173 (2006.01) G06F 15/80 (2006.01)

Patent

CA 1256581

ABSTRACT A massively parallel processor is described comprising 65,534 (=216) individual processors organized so that there are 16 (=24 individual processors on each of 4,096 (=212) integrated circuits. The integrated circuits are interconnected in the form of a Boolean cube of 12 dimensions for routing of message packets. Each circuit board carries 32 (=25) integrated circuits and each backplane carries 16 (=24) circuit boards. There are eight (=23) backplanes advantageously arranged in a cube that is 2x2x2. Each integrated circuit on a circuit board is connected to five integrated circuits on the same board which are its nearest neighbors in the first five dimensions. Further, each integrated circuit is also connected to four other integrated circuits on different circuit boards, but on the same backplane; Finally, each integrated circuit is also connected to three other integrated circuits, each on a different backplane. As a result of this arrangement, all message packets are first routed to nearest neighbor ICs located on the same circuit board; all message packets are then routed to nearest neighbor ICs located on the same backplane; and finally all message packets are then routed to nearest neighbor ICs located on different backplanes.

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