Method and apparatus for isolating faults in a digital logic...

Details Method and apparatus for isolating faults in a digital logic... Method and apparatus for isolating faults in a digital logic...

G - Physics

06

F

354/1

G06F 11/26 (2006.01) G01R 31/3183 (2006.01) G06F 11/22 (2006.01)

Patent

CA 1273706

ABSTRACT OF THE INVENTION The method and apparatus for isolating faults in circuitry of a digital computer includes the use of a fault isolation gen- eration program which provides a data base containing a list of possible faulty components for each cycle of the computer's clock for execution by a service processor of the actual computer dur- ing testing. The fault isolation generation program is generated by using a simulator loaded with a mathematical model of the actual computer in connection with the execution of the diagnos- tic program executed on the actual computer during testing. The fault isolation program generates a list of circuit elements capable of generating fault indications, excluding circuit ele- ments not capable of generating such fault indications.

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