H - Electricity – 03 – L
Patent
H - Electricity
03
L
H03L 7/089 (2006.01)
Patent
CA 2474111
The delay of a section or sections within a delay line is controlled via a secondary low-speed dual-direction delay-line. This secondary delay line is adjusted via a conventional phase-detector, and functions primarily as a dual-direction shift register, but may have a small number of stages which maintain analog voltages between digital equivalents. The mixed-signal control bits/nets can partially switch small capacitances onto the primary delay-line, adjusting the delay in arbitrarily small increments. This approach performs the low-pass filtering required in either analog or digital DLLs/PLLs, yet is smaller, and more power efficient than either. It also prevents the fitter in the output of digital DLLs/PLLs caused when the delay line control switches between distinct digital states. Further, it can be implemented entirely with conventional digital logic, making it attractive for use in integrated circuits/systems wherever synchronization and clock multiplication are necessary.
Allan Gordon John
Smart & Biggar
LandOfFree
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