Method and apparatus for optimizing inter-processor...

Details Method and apparatus for optimizing inter-processor... Method and apparatus for optimizing inter-processor...

G - Physics

06

F

354/233

G06F 13/42 (2006.01) G06F 9/38 (2006.01)

Patent

CA 1321658

606096 A METHOD AND APPARATUS FOR OPTIMIZING INTER-PROCESSOR INSTRUCTION TRANSFERS ABSTRACT A protocol for transferring instructions between asynchronous processors in a computer system is provided. Each instruction transfer requires the transfer of an opcode and a variable number of operands. The transfer is accomplished via a bus which interconnects the processors. The opcode and operands are assembled in a buffer in the sending processor and then transferred to the receiving processor in reverse order, i.e., operands first and opcode last. The receiving processor does not acknowledge any of the transfers until it receives the opcode which is always sent last. Upon receipt of the opcode, the receiving processor knows the instruction transfer is complete and sends the acknowledge signal immediately thereafter. PD88-0418 U.S.: DIGQ:019/DIGK:035 FOREIGN: DIGW:019

606096

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