G - Physics – 06 – F
Patent
G - Physics
06
F
354/234
G06F 9/38 (2006.01) G06F 12/10 (2006.01) G06F 13/18 (2006.01)
Patent
CA 1325285
METHOD AND APPARATUS FOR ORDERING AND QUEUEING MULTIPLE MEMORY REQUESTS ABSTRACT In a pipelined computer system, memory access functions are simultaneously generated from a plurality of different locations. These multiple requests are passed through a multiplexer 50 according to a prioritization scheme based upon the operational proximity of the request to the instruction currently being executed. In this manner, the complex task of converting virtual-to-physical addresses is accomplished for all memory access requests by a single translation buffer 30. The physical addresses resulting from the translation buffer 30 are passed to a cache 28 of the main memory 14 through a second multiplexer 40 according to a second prioritization scheme based upon the operational proximity of the request to the instruction currently being executed. The first and second prioritization schemes differ in that the memory is capable of handling other requests while a higher priority "miss" is pending. Thus, the prioritization scheme temporarily suspends the higher priority request while the desired data is being retrieved from main memory 14, but continues to operate on a lower priority request so that the overall operation will be enhanced if the lower priority request hits in the cache 28.
610687
Hetherington Ricky C.
Murray John E.
Webb David A. Jr.
Digital Equipment Corporation
Hetherington Ricky C.
Murray John E.
Smart & Biggar
Webb David A. Jr.
LandOfFree
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