Method and apparatus for power throttling a processor in an...

G - Physics – 06 – F

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G06F 1/32 (2006.01)

Patent

CA 2667422

A power system couples to a multi-core processor to provide power to the processor. The power system throttles at least one of the cores of the processor when the power that the processor consumes from thepower systemexceeds a predetermined threshold power. The power systemmay reduce the rate of instruction issue by a particular core or clock gate a particular core to provide power throttling. The power system dynamically responds to variance of the actualoutput voltage that processor circuitryreceives from the power system in comparison to an expected output voltage over time and corrects for such variance.

L'invention concerne un système d'alimentation couplé à un processeur à noyaux multiples pour alimenter le processeur. Le système de puissance réduit au moins un des noyaux du processeur lorsque la puissance du système d'alimentation consommée par le processeur dépasse un seuil prédéterminé. Le système d'alimentation réduit le débit de génération d'instructions par un noyau particulier ou porte d'horloge particulière pour réduire la puissance. Le système de puissance répond à la variation de la tension de sortie réelle que le circuit de processeur reçoit du système de puissance par comparaison avec une tension de sortie prévue sur la durée et corrige une telle variation.

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