Method and apparatus for scan testing digital circuits

Details Method and apparatus for scan testing digital circuits Method and apparatus for scan testing digital circuits

G - Physics

01

R

G01R 31/3185 (2006.01)

Patent

CA 2219847

A method and digital system for testing scannable memory and combinational networks. The scannable memory is configurable into several scan chains. Each chain may have a different effective clock rate, as determined by respective clock enable signals. The method and digital system allow scan testing of digital circuits that use a single operational clock rate and several functional clock enable signals to effect slower lock operating rates. The digital system includes memory elements having scan enable and clock enable inputs.

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