Method and apparatus for self-testing of delay faults

Details Method and apparatus for self-testing of delay faults Method and apparatus for self-testing of delay faults

G - Physics

01

R

G01R 23/02 (2006.01) G01R 31/30 (2006.01)

Patent

CA 2099415

-9- METHOD AND APPARATUS FOR SELF-TESTING OF DELAY FAULTS Abstract A method is provided for enabling a digital circuit (12), clocked by a series of pulses, to test itself for delay faults. The method uses delay cells (16,24,36,30,32) to detect delay faults within the digital circuit. A pattern generator (14) supplies a test pattern to the digital circuit Delay cells (16) within the pattern generator are used to detect delay faults associated with two or more inputs. The circuit response is captured and evaluated for correctness. The delay cells are used to capture the response at the correct time to detect delay faults between input(s) and output(s). Two methods are shown - one that depends on the clock period and one that does not.

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