H - Electricity – 04 – L
Patent
H - Electricity
04
L
H04L 29/02 (2006.01)
Patent
CA 2327910
A method and apparatus are disclosed for improving the processing time of reduced complexity sequence estimation techniques, such as reduced state sequence estimation (RSSE). The possible values for the branch metrics in the RSSE are precomputed to permit pipelining and the shortening of the critical path. Precomputing the branch metrics for all possible symbol combinations in the channel memory makes it possible to remove the branch metrics unit (BMU) and decision-feedback unit (DFU) from the feedback loop, thereby reducing the critical path. A look-ahead branch metrics unit (LABMU) and an intersymbol interference canceller (ISIC) precompute the branch metrics for all possible values for the channel memory. At the beginning of each decoding cycle, a set of multiplexers (MUXs) select the appropriate branch metrics based on the survivor symbols in the corresponding survivor path cells (SPCs), which are then sent to an add-compare-select unit (ACSU). The computational load of the precomputations is reduced for multi-dimensional trellis codes by precomputing each dimension of the multi-dimensional trellis code separately. Prefiltering techniques are used to reduce the computational complexity by shortening the channel memory. A hybrid survivor memory architecture is also disclosed for a RSSE for a channel having a channel memory of length L, where the survivors corresponding to the L past decoding cycles are stored in a register exchange architecture (REA), and survivors corresponding to later decoding cycles are stored in a trace-back architecture (TBA) or register exchange architecture (REA). Symbols are mapped to information bits to reduce the word size before being moved from the first register exchange architecture (REA) to the trace-back architecture (TBA) or the second register exchange architecture (REA).
Azadet Kameran
Haratsch Erich Franz
Kirby Eades Gale Baker
Lucent Technologies Inc.
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