H - Electricity – 01 – L
Patent
H - Electricity
01
L
H01L 21/268 (2006.01) G01R 31/28 (2006.01) G01R 31/311 (2006.01) H01L 21/306 (2006.01) H01L 21/3105 (2006.01) H01L 21/477 (2006.01) H01L 21/479 (2006.01) H01L 21/70 (2006.01)
Patent
CA 2098416
The described invention is directed to microwave methods for burning-in, electrical stressing, thermal stressing and reducing rectifying junction leakage current in fully processed semiconductor chips individually and at wafer level, as well as burning in and stressing semiconductor chip packaging substrates and the combination of a semiconductor chip mounted onto a semiconductor chip packaging substrate. Microwaves burn-in devices in a substantially shorter period of time than conventional burn-in techniques and avoid the need for special workpiece holders which are required by conventional stress and burn-in techniques. Additionally, microwave methods are described for reducing the leakage current of rectifying junctions, such as PN junctions and Schottky barrier diode junctions of semiconductor devices on fully processed semiconductor chips and wafers.
Freiermuth Peter E.
Ginn Kathleen S.
Haley Jeffrey A.
Lamaire Susan J.
Lewis David A.
International Business Machines Corporation
Saunders Raymond H.
LandOfFree
Method and apparatus for stressing, burning in and reducing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for stressing, burning in and reducing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for stressing, burning in and reducing... will most certainly appreciate the feedback.
Profile ID: LFCA-PAI-O-1724945