G - Physics – 06 – F
Patent
G - Physics
06
F
G06F 11/10 (2006.01) G06F 11/08 (2006.01)
Patent
CA 2045251
A bus interface between a data bus and data storage devices provides error protection for multi-byte data packets received from the bus and intended for storage on an associated storage device by checking the data symbols in a packet for errors using check sum and parity symbols included in the packet. The bus interface then (i) encodes a predetermined number of data symbols to generate error detection symbols, (ii) again checks the data symbols for errors using the parity bits, and (iii) stores the data and associated error detection symbols in one of a series of linked buffers. Each buffer holds enough the data and associated error detection symbols to fill one storage unit, or sector, on an associated storage medium. A storage interface later retrieves the buffered data and error detection symbols, combines them with the address of a designated storage sector, and encodes the symbols to generate error correction symbols. It then stores the encoded data, and error detection and correction symbols in the designated sector. When the storage interface later retrieves the symbols from the sector, it corrects errors in the data using the retrieved error correction symbols. It next removes the sector address from the error detection symbols and returns the data and error detection symbols to the bus interface. The bus interface (i) generates parity bits, (ii) checks for errors using the error detection symbols, (iii) generates check sum symbols and (iv) transmits the data, check sum and parity symbols over the bus. If the bus interface at any time detects an error, it stops the data transfer operation.
Deroo John E.
Frame Robert C.
Solli Anne
Digital Equipment Corporation
Smart & Biggar
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