Method and apparatus for verifying data processing apparatus

Details Method and apparatus for verifying data processing apparatus Method and apparatus for verifying data processing apparatus

G - Physics

06

F

G06F 9/38 (2006.01) G06F 11/08 (2006.01)

Patent

CA 2105113

Asynchronous computation commands sent from a command control are held in a command queue. The executable command is selected and supplied to a pipelined asynchronous computing unit. A status area is assured for each command held in the command queue and pipeline bits indicative of a progressing state of the execution of the command in the asynchronous computing unit are stored. A queue verifier discriminates the pipeline bits and verifies that a plurality of pipeline stages does not exist in the status area of the same command and that a plurality of pipeline stages does not exist among the commands, thereby guaranteeing the correct order and operation of the execution of the commands.

Des instructions de calcul asynchrones transmises par une unité de commande sont mises en file d'attente. L'instruction à exécuter est sélectionnée et est transmise à une unité de calcul asynchrone pipeline. Une zone de situation est réservée à chaque instruction de la file d'attente et les bits pipeline représentant l'état d'évolution de l'exécution de l'instruction dans l'unité de calcul asynchrone sont stockés. Un vérificateur de file d'attente effectue une discrimination sur les bits pipeline et s'assure de l'absence d'une pluralité d'étages pipeline dans la zone de situation de l'instruction en cause et de l'absence de pluralité d'étages pipeline entre les instructions, ce qui garantit l'ordonnancement exact et la bonne exécution de l'instruction.

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