G - Physics – 11 – C
Patent
G - Physics
11
C
G11C 16/06 (2006.01) G06F 11/16 (2006.01) G11C 16/04 (2006.01) G11C 16/08 (2006.01) G11C 29/00 (2006.01)
Patent
CA 2205733
A redundancy circuit used in a non-volatile memory chip to increase the production yield due to manufacturing defects. The redundancy circuit includes a redundancy predecoder circuit, a source follower EEPROM (electrically erasable programmable read only memory) memory fuse, a scheme to use the column high voltage drivers (also known as page latch) to program the EEPROM fuses, a scheme to use the regular row decoder (also known as wordline driver or x-decoder) as the redundancy row decoder, and an out-of-bound address as a redundancy enable/disable signal.
Circuit de redondance utilisé dans une puce mémoire permanente pour améliorer le rendement en cas de défauts de fabrication. Comprend un circuit prédécodeur de redondance, une mémoire à fusibles EEPROM (mémoire morte programmable effaçable électriquement) à source suiveuse, un plan d'utilisation des circuits d'attaque haute tension de colonne (appelés aussi verrous de page) pour programmer les mémoires à fusibles EEPROM, un plan d'utilisation du décodeur de rangée ordinaire (appelé aussi décodeur-x ou «wordline driver») comme décodeur de ligne de redondance, et une adresse hors limites comme signal de validation/invalidation de redondance.
Blyth Trevor
Tran Hieu Van
Information Storage Devices Inc
Riches Mckenzie & Herbert Llp
LandOfFree
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