Method and arrangement for adapting a clock to a...

H - Electricity – 03 – K

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H03K 5/14 (2006.01) H04L 7/033 (2006.01)

Patent

CA 2010596

ABSTRACT OF THE DISCLOSURE A method and an apparatus for adapting a locally- generated clock having an arbitrary phase relation to a plesiochromic data signal in which further clocks are derived from the clock via a delay line chain in such a fashion that a clock sequence having identical phase spacings is produced. These clocks are clocked by the data signal in edge-triggered D flip-flops. The difference between the logical states of the Q outputs of two neighboring D flip-flops provides a preselection of the best-adapted clock. Proceeding from the Q outputs and Q outputs of the D flip-flops and the non-inverting and inverting outputs of a plurality of amplifiers, a gate arrangement connects an optimally-adapted clock to a clock output. A data signal is delayed in a delay unit by the time that the selection of the optimally adapted clock requires. This then clocks the delayed data signal in an edge-triggered D flip-flop.

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