Method and arrangement for detecting faults in a memory device

Details Method and arrangement for detecting faults in a memory device Method and arrangement for detecting faults in a memory device

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G11C 29/00 (2006.01) G06F 11/07 (2006.01) G11C 29/10 (2006.01) G11C 29/14 (2006.01)

Patent

CA 1073104

TELEFONAKTIEBOLAGET L M ERICSSON, S-126 25 STOCKHOLM SWEDEN METHOD OF AND ARRANGEMENT FOR DETECTING FAULTS IN A MEMORY DEVICE Abstract of disclosure: A method and an arrangement for detecting among faultless memory elements such a faulty memory element out of which the same binary digit is read independent on which of the two binary digits has been written into the element. Two element categories are introduced. If a memory element belongs to the first cate- gory normal writing and reading processes are carried out. If a memory element belongs to the second category the writing processes as well as the reading processes are combined with an inversion of the actual transferred binary information. The category of an clement is shifted at times, for example before each writing process.

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