H - Electricity – 04 – L
Patent
H - Electricity
04
L
328/82
H04L 7/02 (2006.01) H04L 7/033 (2006.01)
Patent
CA 1288829
20365-2773 Abstract Disclosed is a method for recovering the clock and/or the clock phase of a synchronous or plesiochronous digital signal. At the inputs of devices for transmitting or processing digital signals, their clock must be recovered. The new method is intended to provide the possibility for arrangements which can be implemented to the greatest extent by means of logic circuits in "gate arrays" or "cell arrays". In an auxiliary clock generator, an auxiliary clock is generated or auxiliary clocks (HT1,HT2) of the same frequency but different phase relationship extracted from it are generated which, conducted via a phase correction facility, produce an auxiliary data clock (DHT) as recovered clock. In principle, the frequency of this auxiliary clock or of these auxiliary clocks (HT1,HT2) deviates from that of the auxiliary data clock (DHT) to be formed. A phase sensor checks whether the active edges of the digital signal (DS) and of the auxiliary data clock (DHT) have approached each other to less than a defined time interval and emits a correction signal (K) as soon as this is the case. This signal cause a phase shifting of the auxialiary data clock (DHT) to be effected in the phase correction facility by switching between the extracted auxiliary clocks (HT1-HT2) and/or by reversing the polarity of the auxiliary clock or of the extracted auxiliary clocks (HT1,HT2). The method can be used in digital signal multiplex devices and distributor multiplexers.
552695
Aktiengesellschaft Siemens
Fetherstonhaugh & Co.
Volejnik Wilhelm
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