Method and circuit arrangement for checking the observance...

H - Electricity – 04 – L

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H04L 1/24 (2006.01) H04L 12/56 (2006.01) H04Q 1/24 (2006.01)

Patent

CA 2094561

ABSTRACT OF THE DISCLOSURE A check of the observance of prescribed transmission bit rates in an ATM switching equipment occurs using counter devices (RAM1, ALU) working according to the "leaky bucket" principle. These are individual allocated to virtual connections via the switching equipment (VA). The momentary counter readings of these counter devices are respectively decremented by a variable count value only upon arrival of a message cell of the respective virtual connection. This variable count value is proportional to the time difference between the arrival time of the respective message cell and the arrival time of the message cell of the same virtual connection that immediately preceded it. The transmission bit rates determined for the virtual connections are thereby allocated to defined bit rates classes. On the basis of this allocation, an individual proportionality factor that is utilized for the duration of the existence of the respective virtual connection for the calculation of the variable count value is calculated for each of the virtual connections on the basis of this allocation.

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