Method and circuit arrangement for measuring the depletion...

G - Physics – 01 – R

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G01R 31/26 (2006.01) G01K 7/01 (2006.01)

Patent

CA 2126649

A method and a circuit arrangement having a device for measuring the depletion layer temperature of a GTO are specified. In this case, a measurement current (I M) is impressed in the gate circuit, and the voltage (U GR) between the cathode and gate is measured, with an applied measurement current (I M), after the transient turn-off processes have decayed. This voltage (U GR) is at this time dependent on the depletion layer temperature of the GTO. It thus becomes possible to measure the depletion layer temperature directly on the element, that is to say without circuitous routes via a heat sink temperature and calculation of the thermal resistance or the like, and during operation, continuously, and in consequence to monitor and control the stress level on the GTO precisely.

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