Method and circuit for built in self test of phase locked loops

Details Method and circuit for built in self test of phase locked loops Method and circuit for built in self test of phase locked loops

G - Physics

01

R

G01R 31/28 (2006.01) H03L 7/08 (2006.01) H03L 7/18 (2006.01) H03L 7/085 (2006.01) H03L 7/089 (2006.01)

Patent

CA 2220622

A method of testing phase locked loops (PLL) and a testing circuit comprising the steps of applying a normal stimulus signal whose frequency is within the lock range of the PLL to the input of the PLL, substituting the normal input stimulus with an alternative signal derived from an internal feedback of the PLL, adding or deleting one or more cycles from the alternative signal and observing the response of the PLL to the alternative signal. Variations of the method allow for determining Gain-Bandwidth product, lock range, lock time, Bit Error Rate, Jitter and other parameters which can then be compared with predetermined values to determine whether the PLL is properly functional.

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